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CPU cache
Results: 1614

#	Item
781	EVAL: Utilizing Processors with Variation-Induced Timing Errors∗ Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iac Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:20:01 Computer architecture Microprocessors Central processing unit Digital signal processing Fuzzy control system Multi-core processor Control system CPU cache Control theory Computer hardware Computing Control engineering
782	Scalable Cache Miss Handling for High Memory-Level Parallelism Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:12:53 Central processing unit Microprocessors Computer memory CPU cache Cache Runahead Multi-core processor Microarchitecture Memory-level parallelism Computer hardware Computer architecture Computing
783	ReCycle: Pipeline Adaptation to Tolerate Process Variation∗ Abhishek Tiwari, Smruti R. Sarangi and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-11 01:31:00 Electronic engineering Central processing unit Pipeline Hazard Clock distribution network Clock skew Alpha 21264 CPU cache Computer architecture Computer hardware Clock signal
784	BulkCommit: Scalable and Fast Commit of Atomic Blocks in a Lazy Multiprocessor Environment Xuehai Qian, Benjamin Sahelices Josep Torrellas, Depei Qian Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-02-19 00:20:13 Cache Central processing unit Computer memory C dynamic memory allocation Computer architecture Computer hardware Computing CPU cache
785	Volition: Scalable and Precise Sequential Consistency Violation Detection Xuehai Qian, Josep Torrellas Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:41 Cache Central processing unit Parallel computing Computing Volition Computer memory Computer hardware CPU cache
786	Microsoft PowerPoint - HC18.720.S7T2.A Novel Processor Architecture for High-Performance Stream Processing.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:56:09 Computer engineering Instruction set Microarchitecture CPU cache Program counter MIPS architecture Central processing unit Computer hardware Computer architecture
787	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware∗ Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas University of Illinois at Urbana-Champaign {sarangi,atiwari,tor Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:11:09 Microprocessors Central processing unit X86 architecture Multi-core processor Parallel computing Athlon CPU cache P5 Microcode Computer hardware Computer architecture Computing
788	Trace Analysis for Block-level Caching in Cloud Computing Systems Pim Van Riezen, Lennard Zwart {pi,lennard}@cloudvps.com Cloud VPS Dulcardo Arteaga, Ming Zhao Add to Reading List Source URL: www.cloudvps.nl Language: English - Date: 2013-02-26 05:56:46 Cache Computer memory CPU cache Central processing unit Computer storage Solid-state drive IOPS Smart Response Technology Lookup table Computing Computer hardware Computer performance
789	The Design Complexity of Program Undo Support in a General Purpose Processor Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 18:05:40 Computing CPU cache Undo Speculative execution Application checkpointing Rollback Speculative Processor register Computer architecture Computer hardware Central processing unit
790	Microsoft PowerPoint - present_isca11_2 Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-06-30 12:31:41 Josep Torrellas Computer architecture Honda P series CPU cache Application checkpointing Computing Computer hardware

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